The invention is concerned with the manufacture of monolithic integrated solid-state circuits of high packing density employing planar transistors of small dimensions. The invention is based on the Triple-Diffusion Process (3D technology) as known from DE-OS No. 30 09 434 and from the technical journal "Electronics" of Aug. 7, 1975, pp. 104 to 106. This process is characterized by the fact that by means of ion implantations the dopings of the collector region, of the base region and of the emitter region are carried out in succession.
This process, hereinafter briefly referred to as the 3D process, apart from enabling the manufacture of bipolar integrated circuits of high packing density, offers the advantage of dispensing with the high-temperature processes required for depositing an epitaxial layer on to a substrate possibly provided with doping areas for manufacturing buried layers, as well as with the diffusion of insulating zones. These high-temperature processes which are required as a rule for effecting the electrical isolation of the individual transistors, are replaced in the 3D process by one single high-temperature process, namely the collector diffusion process. Finally, there are obtained planar transistors having regions diffused to one another.
The conventional process has disadvantage that the current gain values of the transistors are manufactured in a semiconductor wafer which is later divided into the solid-state circuit are subject to variations differing from wafer to wafer.